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Publications by Sotirios G. Ziavras
Efficient Packet Classification on FPGAs Also Targeting at Manageable Memory Consumption
Resource Management for Dynamically-Challenged Reconfigurable Systems
System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors
Related publications
Fast and Memory-Efficient Traffic Classification With Deep Packet Inspection in CMP Architecture
Packet Classification Using Binary Content Addressable Memory
IEEE/ACM Transactions on Networking
Electronic Engineering
Computer Networks
Communications
Computer Science Applications
Electrical
Software
Memory-To-Memory Connection Structures in FPGAs With Embedded Memory Arrays
Smart-Cache: Optimising Memory Accesses for Arbitrary Boundaries and Stencils on FPGAs
Towards Efficient Virtual Appliance Delivery With Minimal Manageable Virtual Appliances
IEEE Transactions on Services Computing
Information Systems
Computer Networks
Hardware
Communications
Computer Science Applications
Management
Architecture
On Packet Marking at Priority Queues
IEEE Transactions on Automatic Control
Control
Systems Engineering
Computer Science Applications
Electrical
Electronic Engineering
A Scalable Algorithm for Packet Classification
Using Efficient Path Profiling to Optimize Memory Consumption of On-Chip Debugging for High-Level Synthesis
Transactions on Embedded Computing Systems
Hardware
Architecture
Software
Age-Aware Logic and Memory Co-Placement for RRAM-FPGAs
