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Publications by Takao KUDOH
Design of a Parallel VLSI Processor for Road Extraction Based on Logic-In-Memory Architecture
Transactions of the Society of Instrument and Control Engineers
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Parallel Logic Simulation of VLSI Systems
Design of a Content Addressable Memory-Based Parallel Processor Implementing (-1+j)-Based Binary Number System
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Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design
Parallel Algorithms for Inductance Extraction of VLSI Circuits
Parallel Voronoi Diagrams for VLSI Design
Parallel Matrix Multiplication on Memristor-Based Computation-In-Memory Architecture
A SysML and CLEAN Based Methodology for RISC Processor Micro-Architecture Design
International Journal of Embedded and Real-Time Communication Systems
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A Parallel Radix-Sort-Based VLSI Architecture for Finding the First $W$ Maximum/Minimum Values
IEEE Transactions on Circuits and Systems II: Express Briefs
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High-Performance Logic and Memory Devices Based on a Dual-Gated MoS2 Architecture
ACS Applied Electronic Materials
