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Publications by Tezaswi Raja
Transistor Sizing of Logic Gates to Maximize Input Delay Variability
Journal of Low Power Electronics
Electronic Engineering
Electrical
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Delay Analysis of Half Subtractor Using CMOS and Pass Transistor Logic
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Light-Effect Transistor (LET) With Multiple Independent Gating Controls for Optical Logic Gates and Optical Amplification
Frontiers in Physics
Materials Science
Biophysics
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Astronomy
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Physical
Static Induction Transistor Logic
COFFE: Fully-Automated Transistor Sizing for FPGAs
Gate Level Transistor Sizing by Nonlinear Optimization.
Compliance of Reversible Gates in Logic Designing
International Journal of Electrical, Electronics and Computers
Designing Faster CMOS Subthreshold Circuits Using Transistor Sizing and Paralled Transistor Stacks
