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Publications by Wen-Wen Hsieh

A Bus Architecture for Crosstalk Elimination in High Performance Processor Design

2006English

Related publications

A Novel Architecture for a High Performance Data Flow Digital Signal Processor.

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SAGE: An Automatic Analyzing System for a New High-Performance SoC Architecture––processor-In-Memory

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The Design and Evaluation of a Common Bus Memory Access Processor.

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Design of a Multiprocessor High-Bandwidth Communication Gateway Based on a Protocol Processor Pool Architecture

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High Performance Systolic Array Core Architecture Design for DNA Sequencer

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A Scheduling Algorithm for Asymmetric Processor Architecture

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Bus Encoder for Crosstalk Avoidance in RLC Modeled Interconnects

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A System-Level Design Method for Cognitive Radio on a Reconfigurable Multi-Processor Architecture

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