NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Structures

IEEE Journal of Solid-State Circuits - United States
doi 10.1109/jssc.1983.1051937
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Related search

Technology Mapping Algorithms for CMOS Dynamic Logic Circuits.

English

Low-Power Design of Adiabatic Dynamic CMOS Logic Using Parasitic Capacitance of 0.18μm Standard CMOS Model

2017English

Integrated Design of Low-Power Adiabatic Dynamic CMOS Logic Using 0.18μm Standard CMOS Model for Circadian Rhythm OLED Illumination System

International Journal of Control and Automation
ControlSystems Engineering
2017English

A Digit Pipelined Dynamic Time Warp Processor.

1986English

A Notation for Designing Restoring Logic Circuitry in CMOS

Microelectronics Journal
1982English

A Wired-And Current-Mode Logic Circuit Technique in CMOS for Low-Voltage, High-Speed and Mixed-Signal VLSIC

1997English

A Timing Macro Model for Performance Optimization of CMOS Logic Circuits.

English

Design a 10-Bit 100MHz Pipelined ADC Using RB-OTA in 90nm CMOS Technology

IEICE Electronics Express
Electronic EngineeringCondensed Matter PhysicsOpticalElectricalMagnetic MaterialsElectronic
2012English

Background Digital Error Correction Technique for Pipelined Analog-Digital Converters

English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2026 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy