Amanote Research
Register
Sign In
Technology Mapping Algorithms for CMOS Dynamic Logic Circuits.
doi 10.22215/etd/1992-02237
Full Text
Open PDF
Abstract
Available in
full text
Date
Unknown
Authors
Rolando Ramirez Ortiz
Publisher
Carleton University
Related search
Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Electronic Engineering
Computer Graphics
Signal Processing
Applied Mathematics
Electrical
Computer-Aided Design
Performance Analysis of High Speed Domino CMOS Logic Circuits
International Journal of Computer Applications
CMOS-based Carbon Nanotube Pass-Transistor Logic Integrated Circuits
Nature Communications
Astronomy
Genetics
Molecular Biology
Biochemistry
Chemistry
Physics
CMOS VLSI Design of Low Power Comparator Logic Circuits
Asian Journal of Scientific Research
Multidisciplinary
A Timing Macro Model for Performance Optimization of CMOS Logic Circuits.
Logic Testing of Bridging Faults in CMOS Integrated Circuits
IEEE Transactions on Computers
Hardware
Architecture
Mathematics
Computational Theory
Theoretical Computer Science
Software
Novel Logic Circuits Dynamic Parameters Analysis
Neutron-Induced Soft-Error Simulation Technology for Logic Circuits
NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Structures
IEEE Journal of Solid-State Circuits
Electronic Engineering
Electrical
