An Algorithm for Leakage Power Reduction Through IVC in CMOS VLSI Digital Circuits

International Journal of Computer Applications

doi 10.5120/16356-5740

Full Text

Abstract

Available in

Date

Authors

Publisher

Foundation of Computer Science

Related search

Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits

English

A Gate-Level Leakage Power Reduction Method for Ultra-Low-Power CMOS Circuits

English

Design Techniques for Gate-Leakage Reduction in CMOS Circuits

Spanish

Transient Time Slot (TTS) Based Run Time Leakage Reduction Method for Low Power VLSI Circuits

IOSR Journal of VLSI and Signal Processing
2013English

Impact of Gate Induced Drain Leakage on Overall Leakage of Submicrometer CMOS VLSI Circuits

IEEE Transactions on Semiconductor Manufacturing
Electronic EngineeringIndustrialCondensed Matter PhysicsManufacturing EngineeringOpticalElectricalMagnetic MaterialsElectronic
2002English

Performance Comparison of Digital Circuits Using Subthreshold Leakage Power Reduction Techniques

Journal of Engineering Research
Engineering
2017English

CMOS VLSI Design of Low Power Comparator Logic Circuits

Asian Journal of Scientific Research
Multidisciplinary
2014English

Analysis of Leakage Power Reduction Techniques for Low Power VLSI Design

International Journal of Computer Applications
2013English

A New Statistical Method for Maximum Power Estimation in CMOS VLSI Circuits

Active and Passive Electronic Components
Electronic EngineeringOpticalElectricalMagnetic MaterialsElectronic
2000English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2026 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy