Optimizing CMOS Circuits for Low Power Using Transistor Reordering

doi 10.1109/edtc.1996.494152
Full Text
Abstract

Available in full text

Date

Unknown

Authors
Publisher

IEEE Comput. Soc. Press

Related search

Designing Faster CMOS Subthreshold Circuits Using Transistor Sizing and Paralled Transistor Stacks

English

CMOS VLSI Design of Low Power Comparator Logic Circuits

Asian Journal of Scientific Research
Multidisciplinary
2014English

A Gate-Level Leakage Power Reduction Method for Ultra-Low-Power CMOS Circuits

English

Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

VLSI Design
Electronic EngineeringComputer GraphicsHardwareElectricalArchitectureComputer-Aided Design
2010English

Stabilized DC High Voltage Power Supply Using Transistor Circuits

Journal of the Atomic Energy Society of Japan / Atomic Energy Society of Japan
1962English

CMOS-based Carbon Nanotube Pass-Transistor Logic Integrated Circuits

Nature Communications
AstronomyGeneticsMolecular BiologyBiochemistryChemistryPhysics
2012English

Design of Low Power High Speed D-Latch Using Stacked Inverter and Sleep Transistor at 32nm CMOS Technology

International Journal of Trend in Scientific Research and Development
2018English

Temperature-Compensated CMOS Ring Oscillator for Power-Management Circuits

Electronics Letters
Electronic EngineeringElectrical
2007English

Charge Recycling in Power-Gated CMOS Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ElectricalSoftwareComputer GraphicsComputer-Aided DesignElectronic Engineering
2008English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy