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Publications by Ch. Cury
Design of Parallel Prefix Adders Using FPGAs
IOSR journal of VLSI and Signal Processing
Related publications
Design and Implementation of Parallel Prefix Adders Using FPGAs
IOSR Journal of Electronics and Communication Engineering
Evaluation of High Speed and Low Memory Parallel Prefix Adders
IOSR Journal of Electrical and Electronics Engineering
A New Taxonomy for Reconfigurable Prefix Adders
Fast Modular Multiplication Using Parallel Prefix Adder
International Journal of Trend in Scientific Research and Development
Enhancement of Incremental Design for FPGAs Using Circuit Similarity
Design and Performance Analysis of Various Adders and Multipliers Using GDI Technique
International Journal of VLSI Design & Communication Systems
Higher Radix Kogge-Stone Parallel Prefix Adder Architectures
Low Power Digital Signal Processor Architecture for Wireless Sensor Nodes by Using Parallel Prefix Technique
IOSR Journal of Electrical and Electronics Engineering
LUT Based Generalized Parallel Counters for State - Of - Art FPGAs
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