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Publications by G. Saravanakumar

High Speed Low-Power Viterbi Decoder Using Trellis Code Modulation

International Journal of Computing Algorithm
2016English

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An Efficient Low Power Viterbi Decoder Design Using T-Algorithm

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A Two-Stage Decoder for Pragmatic Trellis-Coded M-PSK Modulation Using a Symbol Transformation

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Design of Asynchronous Viterbi Decoder Using Pipeline Architecture

International Journal for Research in Applied Science and Engineering Technology
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Implementation of Reduced Memory Viterbi Decoder Using Verilog HDL

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High Speed Low Complexity Radix-16 Max-Log-Map SISO Decoder

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Low Power Mix Logic Design Using Line Decoder: A Review

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Development of High-Speed and Low-Power Microprocessors Using Superconductive Circuits

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