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Publications by M.V. Sushumna
Design of On-Chip Testing Memory for High Speed Circuits
CVR Journal of Science & Technology
Implementation of BIST Technique for a to D Converters in FPGAs
CVR Journal of Science & Technology
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Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits
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Design Considerations for High Speed Clock and Data Recovery Circuits
Potentials of Chip-Package Co-Design for High-Speed Digital Applications
Limited Switch Dynamic Logic Circuits for High-Speed Low-Power Circuit Design
IBM Journal of Research and Development
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Exploiting Soft Redundancy for Error-Resilient On-Chip Memory Design
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
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Exploiting Soft Redundancy for Error-Resilient On-Chip Memory Design
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High-Speed Single-Electron Memory: Cell Design and Architecture
Distributed ESD Protection for High-Speed Integrated Circuits
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Scheduling and Transport for File Transfers on High-Speed Optical Circuits
Journal of Grid Computing
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