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Publications by O. Coudert
Gate Sizing for Constrained Delay/Power/Area Optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware
Electronic Engineering
Electrical
Architecture
Software
Timing and Design Closure in Physical Design Flows
Related publications
A Power Optimization Method Considering Glitch Reduction by Gate Sizing
Gate Level Transistor Sizing by Nonlinear Optimization.
A Joint Gate Sizing and Buffer Insertion Method for Optimizing Delay and Power in CMOS and BiCMOS Combinational Logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Electrical
Software
Computer Graphics
Computer-Aided Design
Electronic Engineering
Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmings
Delay-Constrained Scheduling: Power Efficiency, Filter Design, and Bounds
Area Optimization Using Structural Modeling for Gate Level Implementation of SPI for Microcontroller
International Journal of Innovative Technology and Exploring Engineering
Mechanics of Materials
Electronic Engineering
Civil
Structural Engineering
Electrical
Computer Science
Power and Area Optimization for Multiple Restricted Multiplication
Design & Optimization of Gate-All-Around Tunnel FET for Low Power Applications
International Journal of Engineering and Technology(UAE)
Architecture
Hardware
Engineering
Chemical Engineering
Biotechnology
Environmental Engineering
Computer Science
Modeling and Sizing Optimization of Hybrid Photovoltaic/Wind Power Generation System
Journal of Industrial Engineering International
Industrial
Manufacturing Engineering
