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Publications by S. Bhunia
Power Reduction in Test-Per-Scan BIST With Supply Gating and Efficient Scan Partitioning
Related publications
Deterministic Partitioning Techniques for Fault Diagnosis in Scan-Based BIST
A Novel Scan Architecture for Power-Efficient, Rapid Test
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
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Flip-Flop Chaining Architecture for Power-Efficient Scan During Test Application
Novel Approach to Reduce Power Droop During Scan-Based Logic BIST
A New Hybrid Test Pattern Generator for Stuck-At –Fault and Path Delay Fault in Scan Based Bist
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