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Publications by Surendra Bohra
Design of Low Power High Speed D-Latch Using Stacked Inverter and Sleep Transistor at 32nm CMOS Technology
International Journal of Trend in Scientific Research and Development
Related publications
Comparative Analysis and Design of Different Type of Low Power High Speed Dynamic Double Latch Comparator Using H-Spice and CMOS Technology
International Journal for Research in Applied Science and Engineering Technology
Design of High-Speed Low-Power Two Level Voltage Converters Using Multi-VTH CMOS Technology
International Journal of Computer Applications
A Low Power, High Speed 18-Transitor True Single-Phase Clocking D Flip- Flop Design in 90nm Cmos Technology
International Journal of Innovative Technology and Exploring Engineering
Mechanics of Materials
Electronic Engineering
Civil
Structural Engineering
Electrical
Computer Science
A Stacked Inverter-Based CMOS Power Amplifier in 65nm CMOS Process
Design a Low Power Half-Subtractor Using .90µm CMOS Technology
IOSR journal of VLSI and Signal Processing
Variable Supply-Voltage Scheme for Low-Power High-Speed CMOS Digital Design
IEEE Journal of Solid-State Circuits
Electronic Engineering
Electrical
Optimizing CMOS Circuits for Low Power Using Transistor Reordering
Design and Analysis of Low Power Analog to Digital Converter Using CMOS Technology
IARJSET
Design of Low Power SAR ADC for ECG Using 45nm CMOS Technology
International Journal of VLSI Design & Communication Systems
