Amanote Research
Register
Sign In
Discover open access scientific publications
Search, annotate, share and cite publications
Publications by Tushar Gupta
Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders With Fully-Parallel Processing Units
Related publications
A Novel Architecture for Elementary-Check-Node Processing in Nonbinary LDPC Decoders
IEEE Transactions on Circuits and Systems II: Express Briefs
Electronic Engineering
Electrical
Energy-Efficient Data Representation in LDPC Decoders
Electronics Letters
Electronic Engineering
Electrical
Conditional Termination Check Min-Sum Algorithm for Efficient LDPC Decoders
IEICE Electronics Express
Electronic Engineering
Condensed Matter Physics
Optical
Electrical
Magnetic Materials
Electronic
LDPC Decoders With Informed Dynamic Scheduling
IEEE Transactions on Communications
Electronic Engineering
Electrical
Augmented Decoders for LDPC Codes
Eurasip Journal on Wireless Communications and Networking
Computer Networks
Computer Science Applications
Signal Processing
Communications
A Parallel-Layered Belief-Propagation Decoder for Non-Layered LDPC Codes
Journal of Communications
Electronic Engineering
Electrical
A Flexible LDPC/Turbo Decoder Architecture
Journal of Signal Processing Systems
Control
Systems Engineering
Information Systems
Signal Processing
Simulation
Hardware
Architecture
Modeling
Theoretical Computer Science
Parallel Interleaver Architecture With New Scheduling Scheme for High Throughput Configurable Turbo Decoder
VLSI Decoder Architecture for High Throughput, Variable Block-Size and Multi-Rate LDPC Codes