Performance Analysis of High Speed Domino CMOS Logic Circuits

International Journal of Computer Applications
doi 10.5120/17371-7905
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Foundation of Computer Science

Related search

An Optimization Method for NBTI-aware Design of Domino Logic Circuits in Nano-Scale CMOS

IEICE Electronics Express
Electronic EngineeringCondensed Matter PhysicsOpticalElectricalMagnetic MaterialsElectronic
2011English

A Timing Macro Model for Performance Optimization of CMOS Logic Circuits.

English

A High Speed and Leakage-Tolerant Domino Logic for High Fan-In Gates

2005English

Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Electronic EngineeringComputer GraphicsSignal ProcessingApplied MathematicsElectricalComputer-Aided Design
2009English

Technology Mapping Algorithms for CMOS Dynamic Logic Circuits.

English

CMOS VLSI Design of Low Power Comparator Logic Circuits

Asian Journal of Scientific Research
Multidisciplinary
2014English

Logic Testing of Bridging Faults in CMOS Integrated Circuits

IEEE Transactions on Computers
HardwareArchitectureMathematicsComputational TheoryTheoretical Computer ScienceSoftware
1998English

CMOS-based Carbon Nanotube Pass-Transistor Logic Integrated Circuits

Nature Communications
AstronomyGeneticsMolecular BiologyBiochemistryChemistryPhysics
2012English

Limited Switch Dynamic Logic Circuits for High-Speed Low-Power Circuit Design

IBM Journal of Research and Development
Computer Science
2006English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy