Amanote Research
Register
Sign In
Exploring SOI Device Structures and Interconnect Architectures for Low-Power High-Performance Circuits
IEE Proceedings - Computers and Digital Techniques
doi 10.1049/ip-cdt:20020451
Full Text
Open PDF
Abstract
Available in
full text
Date
January 1, 2002
Authors
R. Zhang
K. Roy
C.-K. Koh
D.B. Janes
Publisher
Institution of Engineering and Technology (IET)
Related search
CrossNets: High-Performance Neuromorphic Architectures for CMOL Circuits
Annals of the New York Academy of Sciences
Genetics
Molecular Biology
Biochemistry
Neuroscience
History
Philosophy of Science
Double-Gate Fully-Depleted SOI Transistors for Low-Power High-Performance Nano-Scale Circuit Design
Inherently Lower-Power High-Performance Superscalar Architectures
IEEE Transactions on Computers
Hardware
Architecture
Mathematics
Computational Theory
Theoretical Computer Science
Software
A Study of Optimization Techniques for 3D Networks-On-Chip Architectures for Low Power and High Performance Applications
International Journal of Computer Applications
Ambipolar Reduction Methodology for SOI Tunnel FETs in Low Power Applications: A Performance Report
International Journal of Recent Technology and Engineering
Engineering
Management of Technology
Innovation
Architectures for High Dynamic Range, High Speed Image Sensor Readout Circuits
Limited Switch Dynamic Logic Circuits for High-Speed Low-Power Circuit Design
IBM Journal of Research and Development
Computer Science
Development of High-Speed and Low-Power Microprocessors Using Superconductive Circuits
IEEJ Transactions on Fundamentals and Materials
Electronic Engineering
Electrical
Power – Performance Optimization for Custom Digital Circuits
Lecture Notes in Computer Science
Computer Science
Theoretical Computer Science
