Minimizing Power Consumption in CMOS Full Subtractor Using SVL Technique

International Journal of Computer Applications
doi 10.5120/19348-1071
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Foundation of Computer Science

Related search

A Novel Design of SET-CMOS Half Subtractor and Full Subtractor

International Journal of Computer Applications
2015English

Design a Low Power Half-Subtractor Using .90µm CMOS Technology

IOSR journal of VLSI and Signal Processing
2013English

Area Efficient Full Subtractor Based on Static 125nm CMOS Technology

International Journal of Trend in Scientific Research and Development
2018English

High Performance Low Leakage Power Full Subtractor Circuit Design Using Rate Sensing Keeper

International Journal of Research in Engineering and Technology
2014English

Minimizing Power Consumption in Virtualized Cellular Networks

2018English

Delay Analysis of Half Subtractor Using CMOS and Pass Transistor Logic

International Journal of Computer Applications
2016English

A New Technique for Leakage Power Reduction in CMOS Circuit by Using DSM

International Journal of Computer Applications
2017English

A Novel Low Power Adder-Subtractor Using Efficient XOR Gates

Journal of Applied Sciences
2014English

Hazards and Glitch Power Reduction of CMOS Full Adder in 90nm Technology

CVR Journal of Science & Technology
2014English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2025 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy