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Publications by Alex Orailoglu

A Novel Scan Architecture for Power-Efficient, Rapid Test

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Computer Science ApplicationsComputer GraphicsComputer-Aided DesignSoftware
2002English

Predictable Execution Adaptivity Through Embedding Dynamic Reconfigurability Into Static MPSoC Schedules

2007English

Related publications

Flip-Flop Chaining Architecture for Power-Efficient Scan During Test Application

2005English

Double-Tree Scan: A Novel Low-Power Scan-Path Architecture

English

Power Reduction in Test-Per-Scan BIST With Supply Gating and Efficient Scan Partitioning

English

IPStash: A Power-Efficient Memory Architecture for IP-lookup

English

Investigation of a Novel Common Subexpression Elimination Method for Low Power and Area Efficient DCT Architecture

The Scientific World Journal
BiochemistryMedicineGeneticsMolecular BiologyEnvironmental Science
2014English

On Minimization of Peak Power for Scan Circuit During Test

2009English

A Novel Architecture for Efficient Key Management in Humanware Applications

2009English

On the Power for Linkage Detection Using a Test Based on Scan Statistics

Biostatistics
MedicineUncertaintyStatisticsProbability
2005English

Stacked FSMD: A Power Efficient Micro-Architecture for High Level Synthesis

English

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