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Publications by K.S.S.K. Rajesh
CMOS VLSI Design of Low Power Comparator Logic Circuits
Asian Journal of Scientific Research
Multidisciplinary
Related publications
Adiabatic Logic Circuits for Low Power VLSI Applications
International Journal of Science and Research (IJSR)
Low Power Magnitude Comparator Circuit Design
International Journal of Computer Applications
Design and Implementation of Ternary Logic Circuits for VLSI Applications
International Journal of Innovative Technology and Exploring Engineering
Mechanics of Materials
Electronic Engineering
Civil
Structural Engineering
Electrical
Computer Science
Low-Power Design of Adiabatic Dynamic CMOS Logic Using Parasitic Capacitance of 0.18μm Standard CMOS Model
A New Statistical Method for Maximum Power Estimation in CMOS VLSI Circuits
Active and Passive Electronic Components
Electronic Engineering
Optical
Electrical
Magnetic Materials
Electronic
An Algorithm for Leakage Power Reduction Through IVC in CMOS VLSI Digital Circuits
International Journal of Computer Applications
Limited Switch Dynamic Logic Circuits for High-Speed Low-Power Circuit Design
IBM Journal of Research and Development
Computer Science
Cascadable Adiabatic Logic Circuits for Low-Power Applications
IET Circuits, Devices and Systems
Control
Systems Engineering
Electrical
Electronic Engineering
Optimizing CMOS Circuits for Low Power Using Transistor Reordering
