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Publications by M. O. Esonu
Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison With CMOS & BiCMOS Circuits
VLSI Design
Electronic Engineering
Computer Graphics
Hardware
Electrical
Architecture
Computer-Aided Design
Related publications
Performance Analysis of High Speed Domino CMOS Logic Circuits
International Journal of Computer Applications
Testability Analysis Considerations of Digital Circuits.
Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Electronic Engineering
Computer Graphics
Signal Processing
Applied Mathematics
Electrical
Computer-Aided Design
Technology Mapping Algorithms for CMOS Dynamic Logic Circuits.
CMOS VLSI Design of Low Power Comparator Logic Circuits
Asian Journal of Scientific Research
Multidisciplinary
Logic Testing of Bridging Faults in CMOS Integrated Circuits
IEEE Transactions on Computers
Hardware
Architecture
Mathematics
Computational Theory
Theoretical Computer Science
Software
Design and Optizimation of Fast Adder Circuits Using Mixed CMOS Logic Styles
Current and Delay Estimation in Deep Sub-Micrometer CMOS Logic Circuits
CMOS-based Carbon Nanotube Pass-Transistor Logic Integrated Circuits
Nature Communications
Astronomy
Genetics
Molecular Biology
Biochemistry
Chemistry
Physics
