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Publications by Raymond Chow
Gate Level Transistor Sizing by Nonlinear Optimization.
Structural Form as Morphogenetic Event
Related publications
A Power Optimization Method Considering Glitch Reduction by Gate Sizing
Gate Sizing for Constrained Delay/Power/Area Optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware
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Electrical
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Software
Transistor Sizing for Radiation Hardening
Design Optimization of NEMS Switches for Suspended-Gate Single-Electron Transistor Applications
IEEE Transactions on Nanotechnology
Electronic Engineering
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Computer Science Applications
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Comparitive Analysis of Power Optimization Using Mtcmos, Transistor Sizing & Combined Technique on 180nm Technology
IOSR journal of VLSI and Signal Processing
Molecular Floating-Gate Single-Electron Transistor
Scientific Reports
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COFFE: Fully-Automated Transistor Sizing for FPGAs
Designing Faster CMOS Subthreshold Circuits Using Transistor Sizing and Paralled Transistor Stacks
The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor
Nanoscale Research Letters
Materials Science
Nanotechnology
Condensed Matter Physics
Nanoscience
