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Publications by T. Larrabee
Logic Testing of Bridging Faults in CMOS Integrated Circuits
IEEE Transactions on Computers
Hardware
Architecture
Mathematics
Computational Theory
Theoretical Computer Science
Software
Charge-Based Fault Simulation for CMOS Network Breaks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Electrical
Software
Computer Graphics
Computer-Aided Design
Electronic Engineering
Related publications
CMOS-based Carbon Nanotube Pass-Transistor Logic Integrated Circuits
Nature Communications
Astronomy
Genetics
Molecular Biology
Biochemistry
Chemistry
Physics
Investigation of Intermittent Resistive Faults in Digital CMOS Circuits
Journal of Circuits, Systems and Computers
Hardware
Electronic Engineering
Electrical
Architecture
Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Electronic Engineering
Computer Graphics
Signal Processing
Applied Mathematics
Electrical
Computer-Aided Design
Performance Analysis of High Speed Domino CMOS Logic Circuits
International Journal of Computer Applications
Technology Mapping Algorithms for CMOS Dynamic Logic Circuits.
Laser Testing of Integrated Circuits
IEEE Journal of Solid-State Circuits
Electronic Engineering
Electrical
CMOS VLSI Design of Low Power Comparator Logic Circuits
Asian Journal of Scientific Research
Multidisciplinary
The Effects of Transistor Source-To-Gate Bridging Faults in Complex CMOS Gates
IEEE Journal of Solid-State Circuits
Electronic Engineering
Electrical
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy
