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Publications by Khemraj Deshmukh
Study of Design and Analysis of Low-Power 10-Transistor Full Adders Using Novel XOR–XNOR Gates
IOSR journal of VLSI and Signal Processing
Related publications
A Novel Low Power Adder-Subtractor Using Efficient XOR Gates
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Low-Power High-Speed Threshold Logic and Its Application to the Design of Novel Carry Lookahead Adders
Design of Low Power High Performance 32 Bit Alu Using Different Adders in 45nm Technology
International Journal of Advance Engineering and Research Development
Design and Simulation of Low Power 10T Full Adder Using Cadence 16nM Technology
International Journal for Research in Applied Science and Engineering Technology
Design of Low Power Novel Gate
International Journal of Advances in Signal and Image Sciences
Design and Performance Analysis of Various Adders and Multipliers Using GDI Technique
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Design of Parallel Prefix Adders Using FPGAs
IOSR journal of VLSI and Signal Processing
Design of Low Power High Speed D-Latch Using Stacked Inverter and Sleep Transistor at 32nm CMOS Technology
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Low Power-Area Design of Full Adder Using Self Resetting Logic With GDI Technique
SSRN Electronic Journal
