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Publications by Masaoud Houshmand Kaffashian
An Optimization Method for NBTI-aware Design of Domino Logic Circuits in Nano-Scale CMOS
IEICE Electronics Express
Electronic Engineering
Condensed Matter Physics
Optical
Electrical
Magnetic Materials
Electronic
Related publications
Performance Analysis of High Speed Domino CMOS Logic Circuits
International Journal of Computer Applications
Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS
A Timing Macro Model for Performance Optimization of CMOS Logic Circuits.
CMOS VLSI Design of Low Power Comparator Logic Circuits
Asian Journal of Scientific Research
Multidisciplinary
Congestion-Aware Power Grid Optimization for 3D Circuits Using MIM and CMOS Decoupling Capacitors
Technology Mapping Algorithms for CMOS Dynamic Logic Circuits.
Design and Optizimation of Fast Adder Circuits Using Mixed CMOS Logic Styles
Logic Testing of Bridging Faults in CMOS Integrated Circuits
IEEE Transactions on Computers
Hardware
Architecture
Mathematics
Computational Theory
Theoretical Computer Science
Software
Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Electronic Engineering
Computer Graphics
Signal Processing
Applied Mathematics
Electrical
Computer-Aided Design
