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Publications by Rajani Kuchipudi

Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS

2007English

Related publications

An Optimization Method for NBTI-aware Design of Domino Logic Circuits in Nano-Scale CMOS

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Variability-Conscious Circuit Designs for Low-Voltage Memory-Rich Nano-Scale CMOS LSIs

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Structure Optimization for Timing in Nano Scale FinFET

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A Timing Macro Model for Performance Optimization of CMOS Logic Circuits.

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BTI Impact on Logical Gates in Nano-Scale CMOS Technology

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Novel Low Cost, Double-And-Triple-Node-Upset-Tolerant Latch Designs for Nano-Scale CMOS

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Metrology and Characterization for Extending Silicon CMOS

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A Notation for Designing Restoring Logic Circuitry in CMOS

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Technology Mapping Algorithms for CMOS Dynamic Logic Circuits.

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