Amanote Research
Register
Sign In
Discover open access scientific publications
Search, annotate, share and cite publications
Publications by K.S. Lowe
A Joint Gate Sizing and Buffer Insertion Method for Optimizing Delay and Power in CMOS and BiCMOS Combinational Logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Electrical
Software
Computer Graphics
Computer-Aided Design
Electronic Engineering
