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Publications by K.S. Lowe
A Joint Gate Sizing and Buffer Insertion Method for Optimizing Delay and Power in CMOS and BiCMOS Combinational Logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Electrical
Software
Computer Graphics
Computer-Aided Design
Electronic Engineering
Related publications
Gate Sizing for Constrained Delay/Power/Area Optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware
Electronic Engineering
Electrical
Architecture
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Mitigation of Soft Errors on 65NM Combinational Logic Gates via Buffer Gate
International Journal of VLSI Design & Communication Systems
A Gate-Level Leakage Power Reduction Method for Ultra-Low-Power CMOS Circuits
A Power Optimization Method Considering Glitch Reduction by Gate Sizing
A Class a/B Floating Buffer BiCMOS Power Op-Amp
IEEE Journal of Solid-State Circuits
Electronic Engineering
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Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison With CMOS & BiCMOS Circuits
VLSI Design
Electronic Engineering
Computer Graphics
Hardware
Electrical
Architecture
Computer-Aided Design
Delay and Power Macro-Models for Optimizing ECL Circuits.
Current and Delay Estimation in Deep Sub-Micrometer CMOS Logic Circuits
Optimizing Power Consumption, Area, and Delay in Behavioral Synthesis.
